1. Field
Example embodiments relate to a counter array and an image sensor including the same, and more particularly, to a counter array to reduce power consumption by decreasing the number of bits toggled at one time and to increase an operating margin by improving an occurrence where a voltage decreases due to an instant current change, and an image sensor including the same.
2. Description of Related Art
An image sensor captures an image using the properties of a semiconductor acting upon light. With the development of complementary metal-oxide semiconductor (CMOS) technology, CMOS image sensors using CMOS have spread and are widely utilized. A CMOS image sensor may convert an analog signal output from an active pixel sensor (APS) array into a digital signal. For this conversion, a CMOS image sensor may use an analog-to-digital converter (ADC).
CMOS image sensors may be classified into a single ADC scheme or a column ADC scheme according to implementation of analog-to-digital conversion. The single ADC scheme may convert analog pixel signals output from all columns into digital signals within a given time using a single ADC that operates at high speed. Although the single ADC scheme may reduce a chip area, it has higher power consumption because it operates at higher speed. The column ADC scheme may include simpler ADC circuits provided in each of the columns and the column ADC scheme has lower power consumption as compared to the single ADC scheme. Also, the column ADC may include a counter, for example, an up/down counter. The up/down counter may compare a pixel signal output from an APS array with a ramp signal output from an external ramp signal generator and may count a state transition time with respect to a comparison signal output as a comparison result.
Conventional up/down counters may use a binary coded decimal (BCD) codeword scheme including a plurality of flip-flops. The BCD codeword scheme may use a large number of bits (for example, more than one) that are toggled at one time, thereby increasing an instant current change in the up/down counters. For example, when a counter that outputs a 4-bit BCD codeword performs an up-count operation, if the current output of the counter is “0111”, its next output is “1000”. At this time, a maximum of four bits are toggled in the counter. In other words, a counter that outputs an N-bit BCD codeword may have a maximum of N toggled bits where N is a natural number.
The increase of an instant current change in the counter may cause the operating margin of the counter to decrease when a current drop occurs during a high-speed operation of the counter and may lead to a fault of an image sensor.